This batch is not nearly as interesting as the last. Some time ago I acquired a box of random DEC slides. They were stowed away and forgotten until I dragged out my slide scanner for that last job. The scanner hadn't left my desk yet so I figured I'd take care of these, too.
They appear to be schematics, tables and diagrams meant to accompany some sort of training text. I scanned them in the order I found them, which is surely not the order in which they were meant to be presented. I took note of the handwritten text on each:
01 Intercon: DMA Application Bus Interface Cs
002 Fig 30 Sh1: DMA Application Misc Logic Cs
003 Fig 30 Sh2: DMA Application Misc Logic Cs
004 Fig 29 Sh2: DMA Application Misc I/O Logic Cs
005 Fig 29 DMA Application DC010 Logic Cs
006 Fig 30 DMA Application Misc Logic Cs
007 Tbl 12 DMA Application CSR Definition
008 Fig 31 DMA Application CSR Format
009 Fig 27 DMA Application Device Selection Format
010 Fig 28 DMA Application Interrupt Vector
011 Fig 3 8640
012 Fig 15 DC006
013 Fig 14 DC006
014 DC005 Pins
015 DC004
016 Fig 6 DC003
017 Fig 4
018 Intcon ?
019 Fig 29 sh 2
020 Fig 29
021 Fig 30 sh 1
022 Fig 30 sh 2
023 Fig 30
024 Fig 27
025 Fig 28
026 Table 12
027 Interconnect
028 Fig 31
029 DC002
030 DC010 Simplified Logic Diagram
031 DC004 Simplified Logic Diagram
032 DC004 Logical Invertor Table
033 DC005 Simplified Logic Diagram
034 DC003 Simplified Logic Diagram
035 DC006 Block Diagram
036 DC006 Simplified
037 8641 Transceiver
038 8640 8881 Chips
They appear to be schematics, tables and diagrams meant to accompany some sort of training text. I scanned them in the order I found them, which is surely not the order in which they were meant to be presented. I took note of the handwritten text on each:
01 Intercon: DMA Application Bus Interface Cs
002 Fig 30 Sh1: DMA Application Misc Logic Cs
003 Fig 30 Sh2: DMA Application Misc Logic Cs
004 Fig 29 Sh2: DMA Application Misc I/O Logic Cs
005 Fig 29 DMA Application DC010 Logic Cs
006 Fig 30 DMA Application Misc Logic Cs
007 Tbl 12 DMA Application CSR Definition
008 Fig 31 DMA Application CSR Format
009 Fig 27 DMA Application Device Selection Format
010 Fig 28 DMA Application Interrupt Vector
011 Fig 3 8640
012 Fig 15 DC006
013 Fig 14 DC006
014 DC005 Pins
015 DC004
016 Fig 6 DC003
017 Fig 4
018 Intcon ?
019 Fig 29 sh 2
020 Fig 29
021 Fig 30 sh 1
022 Fig 30 sh 2
023 Fig 30
024 Fig 27
025 Fig 28
026 Table 12
027 Interconnect
028 Fig 31
029 DC002
030 DC010 Simplified Logic Diagram
031 DC004 Simplified Logic Diagram
032 DC004 Logical Invertor Table
033 DC005 Simplified Logic Diagram
034 DC003 Simplified Logic Diagram
035 DC006 Block Diagram
036 DC006 Simplified
037 8641 Transceiver
038 8640 8881 Chips